Introduction
Although jitter and wander are closely related, their effects on networks and devices are very different. Phase fluctuation directly causes bit errors at device inputs through the eye closure mechanism, which in turn causes packet loss. Phase wander does not affect the input stage, but rather the ability of the internal clock function to lock and track the upstream reference. Therefore, it affects the distribution of clock references in networks.
This note is directed to laboratory engineers and field workers unfamiliar with the complexities of jitter and wander, and also to dispel some misunderstandings and avoid misinterpretations regarding measurement setup, implementation, and standards compliance.
As an important technology for digital transmission in the mobile backbone network, the development of Synchronous Ethernet (SyncE) has added physical layer distribution and Ethernet synchronization to Ethernet. However, it is not without problems. As with other transmission technologies, jitter and wander threaten the quality and reliability of high-bandwidth data and video services, especially in mobile networks.
Internationally agreed standards for jitter and wander are clearly essential for equipment and network interoperability. And the need to measure phase fluctuation has recently led the ITU-T to add performance limits for Ethernet Equipment Clocks (EEC) networks and clocks to its G.8262 standard. The existing IEEE 802.3 standard for Ethernet is maintained as a complementary phase fluctuation standard, but it is only relevant for component-level testing, not on network equipment or networks. ITU-T standards now contain the limits and masks for phase and frequency jitter and wander that govern network performance, reinforcing that proper testing according to G.8262 is vital and inevitable.
Measuring phase wander provides crucial information about synchronization quality, especially critical in mobile backhaul networks. These wander measurements are equally important regardless of whether synchronization is carried out at the physical layer in SyncE, or at the packet layer in IEEE 1588v2. In addition to establishing compliance with standard standards, wander results can help diagnose synchronization problems.
With this in mind, Spirent has created this technical report for engineers in the laboratory and those in the field who are unfamiliar with the complexities of jitter and wander, and also to dispel some misunderstandings and avoid misinterpretations regarding measurement setup, implementation, and standards compliance.
What are Jitter and Wander?
Jitter and wander are variations in the instants of telecommunication signals caused by various mechanisms, ranging from component behavior and noise to inherent network action. Any digital network device that processes data or clock signals can potentially synchronize the transmitted signal incorrectly and induce jitter and wander effects in the network.
The term “jitter” is also used more generally, for example to describe variations in the arrival time of Ethernet frames or IP packets.
This technical note only describes the specific case of physical layer signal timing variations.
All network devices generate some degree of jitter and, therefore, the network must operate in its presence. When jitter is excessive, bit errors occur and network performance is affected. Even if the jitter itself does not cause bit errors, it reduces the noise margin of the system, making it more prone to errors.
The effects of jitter seen on an oscilloscope are shown on the right.
High-speed variations (phase variations above 10 Hz) in signal synchronization across a system are called jitter. Low-speed variations in a signal or clock (10 Hz down to micro-Hertz) are called wander. The 10 Hz breakpoint is a long-standing convention in telecommunications.
Although jitter and wander are closely related, their effects on networks and devices are very different. Jitter directly causes bit errors at device inputs through the eye closure mechanism shown above. These bit errors result in lost packets. Wander does not affect the input stage, but rather the ability of the internal synchronization function to lock and track the upstream reference. Therefore, wander affects the distribution of clock references in networks.
Causes of Phase Jitter and Wander
Jitter is always present at the output port of any network element (NE), even if a completely jitter-free signal or digital signal originates or a clock is applied to its input. This is known as jitter generation (from the device), output jitter (from the device), or intrinsic jitter. Intrinsic jitter arises from:
- Clock oscillator behavior: noise, spurs, crosstalk, and drift
- Pattern-dependent delay in encoders and decoders
- Laser and modulator pattern dependence
Wander can arise at many points in a network, and numerous standards have been developed to specify wander generation, transfer, and tolerance limits. The following figure shows the SyncE synchronization architecture, whose operation is covered by the ITU-T G.8262 standard.
At each of the slave clock devices in a network, the device locks to the frequency of the Primary Reference Clock (PRC) by recovering a clock from the incoming physical layer signal. The action of recovering and regenerating the clock reference is an important source of wander in a network. Wander is also caused by very slight differences between reference clocks in the network, or by slow changes in the relative phase of two clock signals due to temperature changes.
It can also be caused by very low-frequency phase noise in a clock oscillator. Noise categories include:
- White phase modulation, commonly associated with amplification stages
- Flicker phase modulation, commonly associated with amplification stages
- White frequency modulation, commonly found in passive resonators, for example, the Caesium Standard
- Flicker frequency modulation, which may be related to physical resonance
- Random walk frequency modulation, which may be associated with impacts, vibrations, or temperature
Phase transients can occur when, for example, a slave clock loses its input reference and no backup is available for some time. During the switching period, a phase error can accumulate.
Additionally, a frequency offset or phase offset can occur when a slave clock loses all external reference sources and enters a holdover mode. In this mode, the clock continues to operate with calibration data built during normal lock operation. Over a period of time, the slave clock may eventually develop frequency drift. Other factors such as aging, temperature, and power supply variations can also contribute.
ITU-T Standards
To ensure interoperability between devices and minimize signal degradation due to jitter and network wander, international standards have been established.
ITU-T standards (G.8261 and G.8262) specify performance limits for phase jitter and wander for networks, NE and EEC and are usually taken as a minimum requirement.
For example, the ITU-T G.8262 standard specifies the maximum amounts of peak-to-peak output jitter (within a bandwidth) permitted by an EEC. This is to ensure that the amount of jitter never exceeds the tolerance level specified for the following EEC. In other words, if the jitter level is excessive, the input circuits of the EEC (clock recovery circuits, etc.) may not have been designed or qualified to work error-free under such conditions.
SyncE Phase Jitter Specifications in G.8262 (in relation to IEEE 802.3 and existing SONET/SDH specifications)
It is a primary requirement of SyncE that it can be connected to any Ethernet interface defined according to IEEE 802.3 requirements. SyncE differs from unsynchronized Ethernet only in its additional requirement to transfer network timing. Apart from network timing transfer, SyncE must be fully interoperable with unsynchronized Ethernet (which currently has a huge installed base).
Annex A of ITU-T standard G.8261, subsections A.2 and A.5, establish the interoperability requirements between Ethernet interfaces designed according to IEEE 802.3 and synchronous interfaces designed according to ITU-T standard G.8262. (See G.8264, sections 9.4.1 and 10.1, for additional discussion on Ethernet and SyncE interoperability). In summary, interoperability requirements separate the “port level” from the “clock level”. The port level refers to data extraction and in this case there is no difference between the two interface definitions and full interoperability is required. The difference is limited to the clock level, where network timing must be recovered from the interface and made available as a reference for other synchronous outputs of the network equipment in which it resides. Timing can be propagated through a chain of 20 clocks as in SDH, and this is the main difference with unsynchronized Ethernet, where all ports are timed from free-running oscillators.
When defining the SyncE interface Jitter specification, the need for interoperability was an essential requirement for the ITU-T Study Group 15, Committee Q.13 (which was assigned responsibility for this specification). IEEE 802.3 defines a procedure for testing the high-frequency phase jitter performance of Ethernet interfaces, both in terms of tolerance and noise generation. The methodologies used in 802.3 are completely different from the traditional approach adopted by the ITU-T for defining jitter performance parameters.
Since it was not possible to translate one approach into an equivalent specification in the other approach, given the overriding need to ensure interoperability, it was decided to specify jitter only up to the frequency of jitter that did not overlap with the 802.3 specification and apply the 802.3 specification for the remaining part of the spectrum. That is why there is no high-band jitter generation specification in G.8262 (i.e., why it does not have a structure similar to SONET/SDH jitter specifications).
Jitter tolerance for 1 Gb/s SyncE interfaces is defined up to 50 kHz, and for 10 Gb/s SyncE interfaces up to 40 kHz. Extending the specification beyond this could result in field interoperability problems between Ethernet and SyncE interfaces.
Interoperability is a requirement stipulated in G.8261 Annex A, primarily A.2 and A.5, which defines the Synchronous Ethernet architecture. The {ITU-T, SG15, Q.13} committee used previous G.813-based specifications to guide the development of jitter requirements, so that all simulation work performed for SDH clock chains could be reused for SyncE.
The relevant quote from Jean-Loup Ferrant, Rapporteur of SG15, Q.13 is: “Delegates of Question 13 agreed that the specification should not overlap the requirements established in IEEE 802.3, but simply exist as an additional specification due to the additional feature of clock chaining, which is the transfer of network timing”.
The non-overlapping and additional nature of testing to G.8262 is supported by the implied sequence of tests: IEEE 802.3 phase jitter tests are performed on both Ethernet and SyncE by component providers, and ITU-T G.8262 tests are performed by SyncE system providers and network operators.